Monday July 10, 2006, PT
Incentia Announces TimeBench, a Timing Environment for Nanometer Designs
New Product Offers Advanced On-Chip-Variation Analysis, Signal Integrity Analysis and Constraint Management
SANTA CLARA, Calif. íV July 10, 2006 íV Incentia Design Systems, Inc., an Electronic Design Automation (EDA) software company that focuses on the timing and synthesis market, today introduced TimeBench, a complete timing analysis, management, and debugging environment for 90 and 65 nanometer designs. TimeBench is built on Incentia's world class static timing tool and addresses the most critical issues facing 90 and 65 nanometer designers: On-Chip-Variation Analysis, Signal Integrity Analysis and Constraint Management.
"TimeBench includes and consolidates everything nanometer designers need in a single software environment," said Arthur Wei, Vice President of Operations at Incentia. "We have received positive feedback from customers, and are pleased to continue our commitment to provide the best-of-the-class timing and design tools."
TimeBench: A Complete Timing Environment
The TimeBench Environment takes Incentia's fast static timing analysis capabilities and adds their advanced On-Chip-Variation (OCV) analysis, accurate and efficient signal integrity analysis, and automated constraint management features.
Traditional OCV uses a constant derating factor and may impose unnecessary performance penalties on nanometer designs. These penalties include reduced performance, larger die sizes, and longer design cycles. Incentia's advanced OCV uses variable derating factors based on logic level and physical location to select the optimal derating factor for each timing path. This results in fewer timing violations, and allows design teams to rapidly achieve timing closure. Advanced OCV provides an effective alternative to the difficult problem of using statistical analysis to model process variations.
Signal Integrity Analysis
TimeBench includes timing and signal integrity analysis in an integrated environment. The signal integrity contains both crosstalk and noise analysis. To eliminate the inaccuracy caused by MVS
(Model Voltage Sources), TimeBench relies on Incentia's proprietary Current-source Current-bias Model (ICCM) for crosstalk analysis. Additionally, traditional net-based crosstalk analysis considers only one delta delay on each net, regardless what timing arc drives the net. TimeBench applies a timing-arc based analysis, and considers different delta delays based on the timing arc that drives the timing path. This gives the most accurate crosstalk analysis results. Noise Analysis is done using a dedicated noise analysis engine that accurately captures the behavior of static noise.
The Constraint Manager consists of a constraint checker, a qualified SDC (Synopsys Design Constraint) writer, and a constraint debugger. The constraint checker checks constraint files for completeness, correctness, and conflicts. It also eliminates redundant constraints. The SDC writer then produces a set of optimized constraints. The constraint debugger allows designers to identify the optimal timing exceptions in complex environments on the fly. These capabilities provide an effective and easy-to-use mechanism to purify and generate qualified constraints and thus greatly shorten total constraint management and timing verification turnaround time.
Price and Availability
The TimeBench release is available now for Sun Solaris (32-bit and 64-bit), Linux (32-bit and AMD 64-bit), and HP (32-bit and 64-bit) platforms. For pricing and availability information, please contact Incentia.
About Incentia Products
Incentia Design Systems, Inc. offers advanced complete timing and synthesis solutions to address the ever-growing design challenges in performance, runtime, and capacity for multi-million-gate, nanometer SoC designs.
TimeCraft™ is a fast full-chip, gate-level static timing analyzer (STA). TimeCraft provides the capability to accurately analyze and close timing on complex SoC designs. Its rich features enable timing verifications at the pre-signoff (ECO iteration) stage and final signoff for all kinds of design applications.
DesignCraft™ is a complete logic synthesis tool with integrated capabilities for optimizing area, power, timing and design-for-testability (DFT). It produces aggressive area reduction and low power results, with advantages in runtime and capacity.
Incentia Design Systems, Inc. is a leading provider of advanced timing and synthesis software that addresses the stringent requirements of runtime, design capacity, timing, area, design-for-testability, power consumption and signal integrity for multi-million-gate semiconductor designs. The company's products are in use at leading fabless IC design, systems, semiconductor and design service companies and have successfully been used to tape out numerous designs in different design applications, such as communications, networking, wireless, chipset, consumer electronics, and multi-media.
Incentia has offices in Santa Clara, California and Hsinchu Science Park, Taiwan, as well as distributors in Japan, China, Korea, India and Israel. For more information, please visit www.incentia.com, email firstname.lastname@example.org or call 408-727-8988.
ValleyPR for Incentia
DesignCraft, DesignCraft Pro and TimeCraft are trademarks of Incentia Design Systems, Inc.
All other trademarks and tradenames are the property of their respective holders.