Synthesis Player, Incentia, Improves Multi-million-gate Design Timing Sign-off and Consistency
TimeCraft Offers 15X Speed Up, VIA Reports Success With Sign-Offs of Multi-million-gate Designs
Yahoo EDA News/Business Wire/ChipMaster News
(06/11/01, 3:19 p.m. EST)
SANTA CLARA, Calif.--(BUSINESS WIRE)--June 11, 2001-- Incentia Design Systems, Inc., a new Electronic Design Automation (EDA) company that offers timing and synthesis solutions, today announced its first product - TimeCraft(TM). TimeCraft is a full-chip gate-level static timing analyzer for timing sign-off. It offers fast run time speed and accurate timing analysis results for high performance deep sub-micron (DSM) system-on-chip (SoC) designs with multi-million gates.
TimeCraft's timing engine is tightly integrated with Incentia's new synthesis products that will be announced soon later this year. It allows designers to use the same timing engine throughout the design, synthesis and tape-out processes for more consistent timing results and more complete comprehension of all timing constraints. Benchmarks confirm that for large designs with complex timing exceptions, TimeCraft runs 15 times on average faster than competing tools.
"Our goal is to offer a complete physically validated synthesis solution, and we believe that using a single consistent timing analysis during design and tape-out improves a multi-million-gate DSM's design's performance. Our first step is introducing TimeCraft. Later this year, we plan to announce a TimeCraft signal integrity option and complementary logic and physical synthesis products,'' said Dr. Ihao Chen, Incentia's president and CEO.
Chen noted, "We have shipped TimeCraft to several customers already.''
What VIA Says about Timing Sign-off with TimeCraft "We have been using TimeCraft as the static timing analyzer to sign off our designs,'' said Benjamin Chiu, Section Manager of Design Methodology at VIA Technologies, Inc., one of world's top fabless IC design companies. "Recently, we used it to verify a 2.4 million gate design containing many latch-based data-paths with complicated clocking schemes, timing constraints and timing exceptions. TimeCraft delivered the sign-off accuracy and demonstrated very impressive run time advantage over other solutions. Feature-wise, it offered special capabilities to deal with latch pass-through mode, multi-frequency clocking, and inter-point and gated clock analysis that greatly facilitate our timing verification. We are very impressed at TimeCraft and will continue to use it for our future designs.''
TimeCraft supports the full set of Synopsys Design Constraints (SDC). It offers unique features and many advanced options beyond the full set of SDC scope. For example, in addition to the regular "time borrowing mode'', TimeCraft provides a more intuitive way to analyze timing in latch-based designs and un-clocked registers using the so-called "pass-through mode''. "Our customers are happy with these features. They are very useful,'' noted Chen.
Why DSM SoC Designs Need New Timing Convergence Solutions
Today's synthesis solutions perform simultaneous logic and physical optimization to achieve timing convergence. While this approach is adequate, the process can be further improved for multi-million-gate DSM SoC designs with complex timing constraints.
Due to run time and capacity limitations, existing synthesis solutions either use different timing engines or can only consider a portion of the timing constraints between the synthesis and the sign-off stages.This timing inconsistency introduces problems in timing convergence and performance results. Incentia's solution is to use a single timing engine that is highly efficient to handle the same set of complex timing constraints at both synthesis and sign-off stages.
Pricing and Availability
TimeCraft is available now. It runs on Sun Solaris (32-bit and 64-bit) and Linux platforms. Pricing begins at $45,000 (USD). It is compatible with popular tool flows from leading EDA companies, such as Synopsys, Cadence, and Avant!. A version of TimeCraft with a signal integrity analysis option will also be available later this year.
Invite to Designers at DAC
Designers are invited to stop by the Incentia floor booth (number 2841) or demo suite (number 7741) at the Design Automation Conference (DAC) (www.dac.com) in Las Vegas, June 18 through 20, to see demonstrations of Incentia synthesis and timing solutions.
About Incentia Incentia Design Systems, Inc., a new Electronic Design Automation (EDA) is addressing deep sub micron timing and synthesis for multi-million-gate DSM SoC designs with stringent power, performance and area requirements. For more information visit www.incentia.com, email email@example.com, or call Incentia at 408-727-8988.
Notes to Editors: Graphic of flow or benchmarks available on request. Acronyms -------- DSM: Deep Sub-micron EDA: Electronic Design Automation SoC: System on Chip TimeCraft is a trademark of Incentia Design Systems, Inc. All trademarks and tradenames are the property of their respective holders.