Incentia Improves Timing Analyzer, Customers Applaud Results

Yahoo Finance/Business Wire

(05/30/03 3:33 p.m. EST)

TimeCraft CPU speedup and memory utilization key to signoff success

SANTA CLARA, Calif.--(BUSINESS WIRE)--May 30, 2003--Incentia Design Systems, Inc., an EDA company in the synthesis and timing market, announced today that it has improved the performance of its full-chip, gate-level Static Timing Analyzer (STA), TimeCraft, for multi-million gate, high-performance designs.

Continuing its lead in analysis speed and capacity for large designs, Incentia's new TimeCraft release improves its runtime up to 5X and reduces memory utilization up to 30% on large designs, when compared to the previous release. TimeCraft's performance gains are the result of the refinement of its proprietary "Incremental Timing Exception Reduction" (ITER) technologies and new techniques for timing path tracing and management. These improvements have greatly reduced customers' turnaround time for ECO timing iterations and final signoff, and increase productivity.

"This new TimeCraft release supports our position as a technology leader in the STA market, remarked Ihao Chen, President & CEO of Incentia. "Our customers are pleased with our speed advantage over competing tools. Now, a 10-million-gate design can be analyzed in less than 30 minutes on a 32-bit platform. "

Customers Praise TimeCraft

"TimeCraft has a speed advantage over competing tools. With it, our timing verification turnaround time has been reduced by up to 10-fold. We are successfully applying TimeCraft to image processing ICs used in our copier and printer products. We are pleased with TimeCraft's speed enhancements, its quality and the resultant productivity improvements for our large SoC designs," remarked Zenji Oka, Manager of CAD Engineering Section, Imaging System LSI Development Center, Ricoh Co., Ltd.

"We have adopted TimeCraft for our design flow because of its speed and capacity advantages over competing tools. It drastically reduces the total verification time on our designs with complex timing constraints. With TimeCraft, we expect to realize a productivity impact on our future SoC designs," noted Yoshio Okamura, Executive Manager of Design Technology Div., LSI Product Technology Unit at Renesas Technology Corp, established on April 1, 2003 as a semiconductor joint venture between Hitachi, Ltd. and Mitsubishi Electric Corporation.

"We have used TimeCraft for the timing iteration and signoff stages of our designs, such as the recent tapeout of a RAID controller chipset fabricated using TSMC 0.18um process. We completed the project ahead of schedule due to TimeCraft's quick turnaround time. We plan to continue to use TimeCraft for our future designs," added Vincent Lin, Assistant Vice President of R&D, Promise Technology, Inc.

More about TimeCraft

TimeCraft is a fast, gate-level, full-chip static timing analyzer for timing signoff and ECO timing iterations for multi-million gate, high-performance designs. It supports both SDF and DSPF flows and takes the full set of Synopsys Design Constraints (SDC). TimeCraft offers rich features required in analyzing different kinds of designs. It has been used to successfully tape out numerous customer designs in chipset, networking, communication, multi-media, and wireless applications.


TimeCraft is available now for Sun Solaris (32-bit and 64-bit), HP (32-bit and 64-bit) and Linux platforms.

About Incentia

Incentia Design System, Inc., is a provider of innovative new-generation timing and logic/physical synthesis solutions that address the stringent requirements in runtime, design capacity, timing, area, DFT, and power consumption of multi-million-gate SoC designs. Incentia's customers are designing products for communications, networking, wireless, chipset, consumer electronics and multimedia markets.

Note to Editors: TimeCraft is a trademark of Incentia Design Systems, Inc. All other trademarks and tradenames are the property of their respective holders.

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