Incentia Announces Physical Synthesis Solution With Unified Timing Analyzer for Multi-Million-Gate Designs
DesignCraft Pro Addresses Timing Closure, Capacity, Turnaround Time
SANTA CLARA, Calif--(BUSINESS WIRE)--May 13, 2002--Incentia Design Systems, Inc., an EDA company in the timing and synthesis market, today announced its entry into the physical synthesis market with a new software product -- DesignCraft Pro(TM).
DesignCraft Pro delivers solutions from RTL to detailed placement with DFT and low power options. It is a natural extension of Incentia"s static timing analyzer, TimeCraft(TM), and logic synthesizer, DesignCraft(TM), both announced last year. All three products use a unified, tape-out proven timing engine to ensure timing consistency between implementation and timing sign-off. Based upon its patented technologies, DesignCraft Pro effectively addresses the issues of timing closure, design capacity, and turnaround time, for multi-million-gate nanometer designs.
"Our goal has always been to provide a complete timing and synthesis solution for nanometer designs," said Dr. Shing-Chong Chang, VP of Product Management of Incentia. "Since the announcements of TimeCraft and DesignCraft products last year, we have had tremendous acceptance of our integrated timing and synthesis tools. Now with DesignCraft Pro, we are strengthening our product offerings for design timing closure between synthesis and layout."
Dr. Chang noted, "We have already shipped DesignCraft Pro to several customers in the multi-media, networking and communication design areas."
What AverLogic Says about DesignCraft Pro
"We believe DesignCraft Pro is very helpful in solving timing closure problems between synthesis and layout. On one of our recent designs, we were struggling with timing closure between synthesis and layout, even though synthesized netlist met the timing. We tried DesignCraft Pro and it proved its competence by shaving two nanoseconds off the most critical path, and we taped out the design successfully," said Becker Sze, Senior Design Manager of AverLogic Technologies, Inc., San Jose, Calif.
More about DesignCraft Pro
Thanks to its patented technology and flexible hierarchical software architecture, DesignCraft Pro runs faster while consuming less memory. It handles designs of up to 5 million gates on 32-bit platform workstations, and runs 2X to 5X faster than alternative solutions while producing superior timing results with setup time, hold time, design rule fix and area recovery, all simultaneously optimized. A 64-bit version is available for larger designs.
During today"s IC implementation flow, one of the most frustrating problems facing designers is the inconsistency of timers between implementation and timing sign-off. Incentia eliminates this frustration by using a unified timing engine from TimeCraft, a customer-proven static timing analyzer with many tapeouts. This provides consistent constraint handling and timing analysis at every step of the design flow: synthesis, placement, optimization and timing sign-off.
In addition, DesignCraft Pro offers rich features for power/ground (PG) routing, IO port optimization and planning, macro placement and floorplanning, various placement obstruction handling and a GUI for layout editing and cross-referencing among source code, schematic, hierarchy and layout views.
DesignCraft Pro supports industry standard formats such as .lib, LEF and GDSII for libraries; SDC for timing constraints; Verilog and VHDL for designs; and DEF and PDEF for layout data.
DesignCraft Pro is shipping now. Pricing begins at $100,000 (USD) for a one-year time-based license. It runs on Sun Solaris 32-bit and 64-bit OS, HPUX-11, and Linux platforms. It is compatible with tool flows from other EDA companies such as Synopsys (Nasdaq: SNPS - News), Cadence (NYSE: CDN - News), and Avant! (Nasdaq: AVNT - News).
Incentia Design System, Inc., an EDA company, addresses timing and synthesis issues of multi-million-gate nanometer SoC designs with stringent performance, area and power requirements.
Incentia"s customers are designing products for communications, wireless, chip-set, consumer electronics and multi-media markets. Marubeni Solutions Corp. represents Incentia in Japan and in Korea Davan Tech Co., Ltd. represents Incentia.
For more information visit www.incentia.com, email firstname.lastname@example.org or call 408-727-8988. Company headquarters are located at 4633 Old Ironsides Dr., Suite 200, Santa Clara, CA 95054.
Notes to Editors:
Incentia will be exhibiting at Design Automation Conference (DAC)
(www.dac.com) Booth 1560.
Acronyms and definitions
ASIC: Application Specific IC
DEF: Design Exchange Format
EDA: Electronic Design Automation
IC: Integrated Circuit
GDSII: chip layout format
GUI: Graphical User Interface
HDL: Hardware Description Language
LEF: Library Exchange Format
.lib: Synopsys library format
PDEF: Physical Design Exchange Format
RTL: Register Transfer Level
SDC: Synopsys Design Constraint
Verilog: Popular HDL language
VHDL: VHSIC (Very High-Speed Integrated Circuit) HDL,
popular HDL language
DesignCraft, DesignCraft Pro and TimeCraft are trademarks of Incentia
Design Systems, Inc. All other companies and products referenced
herein are trademarks or registered trademarks of their respective