Suppliers expand ASIC synthesis capabilities

By Michael Santarini and Richard Goering

EE Times

(02/13/02 11:40 a.m. EST)

SAN MATEO, Calif. - New ASIC synthesis options will debut this week as Incentia Design Systems Inc. rolls out its first physical-synthesis tool and Monterey Design Systems Inc. adds a physical-synthesis capability to a new release of its Sonar physical-prototyping tool. Meanwhile, Synplicity Inc. says it is breaking new ground in timing-driven partitioning.

On the heels of launching its DesignCraft logic-synthesis tool and TimeCraft static timing-analysis tool last year, Incentia this week will release DesignCraft Pro, claiming vast run-time and capacity improvements over competitive physical-synthesis offerings.

The company's timer and synthesizer, introduced last year, are major components of a physical-synthesis solution. But with DesignCraft Pro, Incentia has also rolled a floor planner and a placement tool into the offering.

Ihao Chen, president of Incentia, said the synthesis, timing and placement engines are tightly integrated and key to the functionality of the tool. "We just received a U.S. patent on the integration technology," said Chen. "It allows the tool to perform all physical synthesis extremely fast and instead of having each tool work one after the other, they all work together."

Timing built in

DesignCraft Pro users can enter Verilog or VHDL netlists, constraints in Synopsys Design Constraint format, and ".lib" or LEF and DEF files for hard cores. Designers then can use Incentia's built-in floor planner or a third-party floor planner that outputs DEF or PDEF.

The tool then runs synthesis placement and optimization, guided by its built-in TimeCraft timing engine. Shing-Chong Chang, vice president of product marketing at Incentia, claimed the tool handles designs of up to 5 million gates on 32-bit platform workstations, running 2x to 5x faster than competing solutions. Moreover, said Chang, DesignCraft Pro produces better timing results while simultaneously optimizing setup time, hold time, design rules and area recovery. The company claims the 64-bit version of the tool does not have any capacity limits.

Chang said the tool does not yet have clock tree support, nor is signal integrity analysis built in. But the company expects to release a version supporting both in the near future, he said. Pricing begins at $100,000 for a one-year time-based license. DesignCraft Pro runs on Sun Solaris 32-bit and 64-bit operating systems, HP-UX-11 and Linux platforms.

Synthesis combo

By adding detailed gate-level placement to its Sonar physical-prototyping tool, Monterey Design Systems is claiming to provide a complete physical-synthesis capability in combination with third-party register-transfer-level (RTL) synthesis tools. Further, Sonar version 2.1 can now run as a standalone tool, without Monterey's Dolphin physical-design suite.

Sonar is said to produce physical prototypes in less that 1/25th the time it takes to fully place and route a large chip. It provides feedback on timing, area and power, and also delivers logic restructuring, technology mapping, cell sizing, buffer insertion and postplacement optimization.

But, until now, Sonar stopped short of detailed placement, generating a database that only Dolphin could read. "If you don't have Dolphin, there's nothing you can do with it," said Dave Reed, Monterey's vice president of marketing. "We wanted to make sure people could use Sonar if they don't have a Dolphin environment."

With the addition of physical placement, Reed said, users now get a "full-blown physical-synthesis capability" if they use Sonar in conjunction with a tool such as Synopsys' Design Compiler, obviating the need to purchase Synopsys' Physical Compiler. He said that Sonar 2.1 can handle up to 5 million gates flat.

Sonar 2.1 outputs a ready-to-route physical implementation with power routing and clock tree synthesis. It can feed structural-logic changes back into the RTL synthesis tool. Designs can then be "signed off" for final implementation.

Also new are automatic and interactive postplacement logic optimization; detailed routing of power wires; enhanced IR-drop analysis; optimization for low-power leakage cells; and compatibility with third-party tools through standard formats. Dolphin 2.1 is available now on 32-bit and 64-bit platforms starting at $105,000 per year.

Functional partitioning

Claiming a new methodology for synthesis that beats today's hierarchical top-down and bottom-up approaches, Synplicity has added a technology called Multi-Point synthesis to its Synplify ASIC product, and soon will add it to all its other tools.

"Designers have been forced to partition designs to perform synthesis," said John Gallagher, director of ASIC synthesis product marketing at Synplicity. "But we've gotten to a point in [system-on-chip] design where gate count is absolutely the worst way to partition a design to get the best possible [quality of results]."

With Multi-Point, Gallagher said, users will partition their designs based on functionality and timing, not gate counts. That approach yields better-quality timing and area results, faster run-times, the ability to handle very large designs, ease of project setup and constraint entry, and intelligent handling of intellectual-property blocks, he said.

Unlike a bottom-up flow - where designers partition a chip into blocks, synthesize each one and then stitch them back together again — Multi-Point users start and end with a single project. "It doesn't matter how many hierarchical layers you have in doing your synthesis," said Gallagher. "We consider the top level as your last compile point and everything below that gets automatically synthesized."

The Multi-Point technology creates interface logic models (ILMs) based on user-defined "compile points," or instructions to the synthesis tool for modeling and synthesizing particular portions of a design. "The tool will automatically create and propagate ILMs," said Gallagher. "Once a user defines a compile point and tells the tool how to treat the boundaries — with hard, soft or locked setting — we begin the hierarchical synthesis and automatically create, use and propagate the ILMs."

A "locked" compile point ensures that timing in critical blocks is not affected by the synthesis run. "Soft" and "hard" settings indicate where users want parts of a block's logic to be optimized when it's instantiated into a design.

Multi-Point flow users do language compilation of the HDL code using Synplify ASIC's graphical or text-based TCL environment. Designers then do manual time budgeting, defining compile points. Gallagher said the tool's automatic features take over from there.

Multi-Point will first make its appearance in the 2.3 release of Synplify ASIC this month. The company plans to add the technology to its Synplify Pro FPGA synthesis tool and all its other offerings later on. Synplify ASIC starts at $69,000 for a one-year license, $115,000 for a perpetual license.