High performance, low cost, no compromise

The integrated tool suite from Tanner EDA, Incentia and Aldec is helping a growing ASIC design house keep design costs down and design efficiency high - with no compromise on performance.

In today’s ‘always on’, Internet of Things connected world, RF capability, smart sensors and wireless networking have become standard features in many applications incorporating electronic content. The demand for high performance, mixed signal ASICs continues to grow. Yet, not every new ASIC or SoC is designed for fabrication on the latest ‘bleeding edge’ process technologies. Many thousands of mixed-signal devices are produced on mainstream (or More than Moore) process nodes in foundries worldwide. Motivation for this may be the need for high voltage, a need to meet cost constraints, or because some analog features are simply better suited to larger geometries.

Designers working on such devices do not always need, nor can they afford, the EDA tools from the vendors focused on serving the most advanced process nodes. Fortunately there is a wide range of cost-competitive EDA tools available, offering levels of functionality and performance that are well tuned to the requirements of this segment.

Dresden-based ASIC design services company, Productivity Engineering (PE), is a long time user of the analog and mixed-signal design tools from Tanner EDA. Since 2006, PE has relied on the full Tanner EDA tool suite; including front end design, layout, and verification (including 3D parasitic extraction). Stefan Schubert, PE’s VP IC Design Services remains impressed with the Windows-based, low-cost tools - finding them intuitive, easy to use, and fully capable of meeting their analog design needs.

PE operates primarily in the industrial sector, specialising in digital and mixed-signal designs. Their focus is in the area of man-machine interface, motion control, and sensor-based applications. PE’s differentiator is their ability to offer a cost effective, turnkey service from, concept through IP blocks to production silicon.

In the past year, PE has added three new tools to its design flow. The tools have been fully integrated into PE’s existing Tanner EDA tool suite.

1. DesignCraft digital synthesis package,

2. Riviera-PRO TE digital/functional simulation tool, and

3. Tanner EDA’s enhanced verification package, HiPer Verify.

The DesignCraft and Riviera-PRO TE tools are supplied through partnerships with Incentia and Aldec, respectively and are sold and supported by Tanner EDA . This allows PE and other AMS designers to purchase a proven, integrated solution from one supplier; while also having one source for customer support of the entire suite.

Paul Double, Managing Director of EDA Solutions, Tanner-EDA’s European representative, explained: “Many of our Tanner EDA analog and mixed-signal ASIC design customers have been pushing for advanced digital design tools that can be integrated into our Windows/Linux based environment.”

To date, PE has been relying on a number of legacy tools from Mentor Graphics, primarily for the digital portions of designs. But early last year, PE adopted the DesignCraft digital synthesis tool, as integrated into the Tanner EDA HiPer Silicon A/MS solution. “Our existing tool lacks features for optimizing designs: features that are mainstream in most comparable tools today,” Schubert commented.

DesignCraft is cited to run at a speed of 5 million gates in 2 hours, and PE found the tool to perform at least as well as more expensive equivalents, both in terms of speed and features. “And now we can optimise our designs for power, performance and area,” Schubert added. “The testability features are a real bonus. It is the first time we have had DFT support in a tool. It is something we have always had to do separately before.”

Integrated tool flow

Digital and digital-heavy mixed signal simulation was another task for which PE had been relying on older software. Now PE has invested in the Riviera-PRO TE digital simulator and functional verification tool. Tanner EDA integrated the tool into its HiPer Silicon AM/S tool suite, which also includes the Verilog-AMS mixed-signal analysis tool for co-simulation, and T-Spice for analog simulation.

“The difficulty we had before,” Schubert explained, “is that we always had to leave the Tanner EDA design environment to use the old synthesis tool, and then import the data back.” In addition, the Calibre tool is expensive to maintain.

“The introduction of the Riviera-PRO TE simulator is very welcome,” Schubert said, “primarily because it is fully integrated into the Tanner EDA tool flow, making the design task much easier.” In addition, the Tanner-supplied AMS simulation suite was considerably lower cost than offerings from the mainstream rivals.

But lower cost does not necessarily mean less functionality or performance, Schubert emphasised. Riviera-PRO TE is a mixed language RTL and gate-level simulator. It includes debugging and support of verification methodologies with SystemC and System Verilog, assertion-based verification, transaction level modelling and VHDL/Verilog design rule checking.

Although PE has not made a direct ‘apples for apples’ comparison between the HiPer Simulation A/MS suite and the previous Tanner EDA/Mentor Graphics combination for mixed signal simulation, Schubert finds the new tool suite meets their requirements completely. “We were most pleasantly surprised. The results are well within our expectations in terms of time and accuracy.”

PE has also invested in Tanner EDA’s new HiPer Verify tool suite. Again, the design house had exclusively been using Mentor’s Calibre software for verification. The concern here, however, was that the Process Development Kits (PDKs) or DRC decks produced by the foundries are typically only compatible with the most popular sign off tools, from leading EDA vendors. “The critical factor with HiPer Verify, is that it runs Calibre rules files,” Schubert confirmed. He pointed out that HiPer Verify exploits hierarchical and repetitive features, with an error navigator to locate violations and a one-time correction facility, in order to improve productivity and ensure optimal performance.

PE has adopted a hybrid tool solution for their verification; maintaining a mix of Calibre and HiPer Verify software licenses. HiPer Verify works perfectly well for verifying individual IP blocks, and the price-performance allows us to provide more verification capability across our team. PE continues to use Calibre for whole chip verification, he said. The mixed tool portfolio has allowed us to better align tool capability with the requirements of the design while lowering our overall cost.

Yet Schubert is aware that before too long, its 2010 version of Calibre will be out of date and no longer be supported by the foundries. PE is confident in the HiPer Verify roadmap and the planned performance improvements for the tool.

There were no learning curve issues with using either of the new simulation and synthesis tools or HiPer Verify. “The documentation was very good and our engineers picked them up very quickly,” Schubert said. A few questions on the initial set up and licencing procedures were answered swiftly, enabling a smooth ramp up.

Flying high

Last year, PE became part of the French Serma Group, which is strong in the aerospace market. “This could be an opportunity for us,” Schubert highlighted. Also, he noted that being part of a larger group was helping in terms of better leverage with foundries.

Providing cost-competitive solutions is the key to PE’s future success. Tanner EDA tools not only represent a lower initial outlay than many tools of comparable performance, but they cost considerably less to maintain. “This gives us a competitive advantage as a design services company,” Schubert commented, “And we make no sacrifices in terms of design performance.”